PCIe Endpoint IP Core CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA™ AXI Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers.  It is available to act as a bridge to the standard AMBA™ AXI bus.  Other buses such as AMBA™ AHB and Wishbone are available upon request.

The scalable and flexible core has a modular architecture and a high-performance, low-latency design. It supports x8 link widths and offers bi-directional data rate up to 2GB/s. It supports most advanced PCI Express capabilities, including message signaled interrupts, multiple virtual channels, advanced error reporting, end-to-end cyclic redundancy check, power management features, lane reversal and polarity inversion.

The core has an Application Interface (AIF) layer that makes integration significantly easier by relieving the designer from the complexity of transaction layer packet (TLP) handling. This AIF includes a DMA controller and handles the TLP encoding and decoding, and provides an interface to popular system buses, including Wishbone and AMBA™ AHB, AXI, and AXI4.

The external connection interface from the core conforms to the Intel® PIPE specification, ensuring compatibility with any 8-bit PIPE-compliant physical layer (PHY). The core has been successfully used with PHYs from multiple vendors.

The synchronous, latch-free core design was rigorously verified for compliance with the PCI Express specification, and has passed PCI-SIG certification. The core has been tested for interoperability with multiple motherboards using chipsets from various vendors, and is in use by multiple customers.

See representative implementation results (each in a new pop-up window):

Features

• Compliant with PCI Express Base Specification 1.1
• Implements Transaction, Data Link, and Physical protocol layers in hardware
• Supports x8 link width
• Offers a data rate of 2.5 Gbps per lane
• Supports up to eight Virtual Channels
• Supports lane reversal and polarity inversion
• PCI Configuration space type 0 header
• MSI capability support
• End-to-end cyclic redundancy code (ECRC) generation and checking support
• Advanced Error Reporting capability support
• Configurable TLP data payload size, from 128B to 4kB
• Configurable size for the Transmit Retry and Receive data buffers
• Modular architecture
• Synchronous design

• 64-bit internal datapath at 250MHz

Integration

• Application Interface (AIF) for easier system integration using industry standard bus interfaces (e.g., Wishbone, AMBA™); handles up to 8 DMA channels
• Conforms to standard PIPE interface for compatibility with any 8-bit PIPE-compliant PHY

Certification

• The x1 and x4 versions of this core have passed the PCI-SIG PCI Express compliance tests, and appear on their Integrators List.

Applications

PCI Express is rapidly being adopted for a variety of interconnection applications, including:

• Network servers
• Graphics and multimedia
• Communications and mobile product
• Industrial, automotive, and other embedded systems

Block Diagram

Functional Description

The core is divided into four modules responsible for the Configuration Space, Transaction Layer, Data Link Layer, and Physical Layer MAC.

Configuration Space

Provides a Configuration space register file type 0. In addition to the mandatory functions, numerous extended capabilities are also supported.

Transaction Layer module

Responsible for the assembly and disassembly of transaction layer packets. The transaction layer supports four address spaces: Configuration space, Memory space, I/O space and Message Space. Power management services are supported.

Data Link Layer module

Responsible for link management, data protection and integrity checking, retry and power management services.

Physical Layer MAC module

Implements the logical sub-block of the physical layer. The module is responsible for link training and status monitoring, link width negotiation, lane order negotiation, lane polarity reversal control and power management implementation.

SoC Bus Bridge (Application Interface Module)

The SoC Bus bridging feature is added via an additional module called AIF which adds direct SoC bus connectivity with up to 8 DMA channels fully programmable from both the PCIe and SoC busses. The AIF provides a higher-level interface that makes system integration easier than working at the TLP level. The AIF bridge is available for the standard SoC AMBA™ AXI bus. AMB™ AHB and Wishbone are available upon request.

The Completion Controller automatically handles read and write requests, and sends completions if needed.

The configurable DMA Controller provides up to eight independent DMA channels.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified using Avery’s PCI-Xactor verification tool. Inter-operability has been verified with Intel, nVidia, VIA, and SIS chipsets, and PHYs from Altera and Xilinx has been successfully used by CAST.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:

• ASIC cores: HDL RTL source of the CPXP-EP and CPXP-AIF
  FPGA cores: Post-synthesis EDIF netlist of the CPXP-EP and CPXP-EP-AIF
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, and expected results
• Synthesis or place and route script
• Comprehensive user documentation

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx