Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream

Octal SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Data Link Controllers
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES, programmable
Key Expander

DES single
DES triple

Hash Functions
SHA-3 (Keccak)

  • Compliant with PCI Express Base Specification 1.1
  • Implements Transaction, Data Link, and Physical protocol layers in hardware
  • Supports x8 link width
  • Offers a data rate of 2.5 Gbps per lane
  • Supports up to eight Virtual Channels
  • Supports lane reversal and polarity inversion
  • PCI Configuration space type 0 header
  • MSI capability support
  • End-to-end cyclic redundancy code (ECRC) generation and checking support
  • Advanced Error Reporting capability support
  • Configurable TLP data payload size, from 128B to 4kB
  • Configurable size for the Transmit Retry and Receive data buffers
  • Modular architecture
  • Synchronous design
  • 64-bit internal datapath at 250MHz


  • Application Interface (AIF) for easier system integration using industry standard bus interfaces (e.g., Wishbone, AMBA™); handles up to 8 DMA channels
  • Conforms to standard PIPE interface for compatibility with any 8-bit PIPE-compliant PHY

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone
  • PCIEXPAIF Application Interface Core for Altera and Xilinx FPGA PCIe Hard IP


The core is designed to work with any 8-bit PIPE-compliant physical layer (PHY). Internal testing and customer experienceshave verified the x1/x4/x8 cores with PHYs from several sources, including:
Altera, ARM, Genesys Logic, Jmicron, NXP, Snowbush, and Xilinx.

PCIe Development Boards

PCIe development boardWe conduct physical interoperability testing with systems and boards from a variety of trusted vendors, including Agilent, Altera, Dini Group, Hardi (now Synplicity) and Genesys Logic. Please

PCIe Chipset Interoperability

While the core is rigorously designed to conform to the specification, we verify this through real-world testing with popular host chipsets, includingintel chipset:
• Intel I915
• Intel I945
• Intel I965
• Intel I975
• nVidia nForce 430
• nVidia nForce 550
• nVidia nForce 570 SLI
• nVidia nForce 590 SLI
• nVidia MPC55 Tritium
• nVidia MPC61nvidea chipset
• nVidia C55 Tritium
• VIA PT890Pro
• SIS 986
• SIS 671FX


Avoiding unexpected challenges in PCI Express core integration, April, 2006, Embedded Computing Design


Download our DATE 06 slides: PCI Express Core Integration with the OCP Bus

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA™ AXI Core

Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers.  It is available to act as a bridge to the standard AMBA™ AXI bus.  Other buses such as AMBA™ AHB and Wishbone are available upon request.

The scalable and flexible core has a modular architecture and a high-performance, low-latency design. It supports x8 link widths and offers bi-directional data rate up to 2GB/s. It supports most advanced PCI Express capabilities, including message signaled interrupts, multiple virtual channels, advanced error reporting, end-to-end cyclic redundancy check, power management features, lane reversal and polarity inversion.

The core has an Application Interface (AIF) layer that makes integration significantly easier by relieving the designer from the complexity of transaction layer packet (TLP) handling. This AIF includes a DMA controller and handles the TLP encoding and decoding, and provides an interface to popular system buses, including Wishbone and AMBA™ AHB, AXI, and AXI4.

The external connection interface from the core conforms to the Intel® PIPE specification, ensuring compatibility with any 8-bit PIPE-compliant physical layer (PHY). The core has been successfully used with PHYs from multiple vendors.

The synchronous, latch-free core design was rigorously verified for compliance with the PCI Express specification. The core has been tested for interoperability with multiple motherboards using chipsets from various vendors, and is in use by multiple customers.

See representative implementation results (each in a new pop-up window):

PCIe core ASIC numbers PCIe core Altera numbersPCIe core Xilinx numbers


PCI Express is rapidly being adopted for a variety of interconnection applications, including:

Block Diagram

cpxp-epx8 block diagram


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


The core has been verified using Avery’s PCI-Xactor verification tool. Inter-operability has been verified with Intel, nVidia, VIA, and SIS chipsets, and PHYs from Altera and Xilinx has been successfully used by CAST.


The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:


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