CAST CPXP-EPX8 Core — XILINX FPGA Results

Results are shown below (at the required frequency of 250 MHz, with a single VC, no ECRC, max. payload 128B, 2kB Retry buffer and 4kB Receive buffer). Actual slice count is dependent on percentage of unrelated logic – see Mapping Report File for details. And, only PCI Express bus interface signals are routed off-chip for IOB results.

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