The following sample results were obtained at the required frequency of 250 MHz, and with a single Virtual Channel (VC0), Maximum Payload of 256B, a 4kB Retry buffer, a 4kB Receive buffer, no ECRC, and using a generic Application Interface.
| Link Width | Technology | Approx. Area |
| x8 | TSMC 0.13 µm | 77,600 gates |
| x8 | TSMC 0.18µm | 83,700 gates |
| x8 | TSMC 0.90 µm | 65,000 gates |
The core includes an SoC bus bridging module (AIF), an additional subsystem that may be used to integrate the core with SoC designs using custom or various standard interfaces. The sample implementation results shown below show the additional gates needed for an AMBA™ AXI with two DMA channels.
| DMA Channels | Technology | Approx. Area |
| 2 DMAs | TSMC 0.13 µm | 23,500 gates |
| 2 DMAs | TSMC 0.18µm | 22,900 gates |
| 2 DMAs | TSMC 0.90 µm | 20,000 gates |