The following sample results were obtained at the required frequency of 250 MHz, and with a single Virtual Channel (VC0), Maximum Payload of 128B, a 2kB Retry buffer, a 4kB Receive buffer, no ECRC, and using a generic Application Interface.
| Altera Device |
ALUTs | Memory | Memory Bits | GXB | I/Os (Only PCIe related pins routed off-chip) |
Quartus |
| Stratix-II GX EP2SGX90-3 |
10498 | 12 M4Ks | 49408 | 8 | 35 | 7.2 |
The core includes an SoC bus bridging module (AIF), an additional subsystem that may be used to integrate the core with SoC designs using custom or various standard interfaces. The sample implementation results shown below show the additional gates needed for an AMBA™ AXI with one DMA channel and 128B completion buffer.
| Altera Device |
ALUTs | Memory | Memory Bits | GXB | I/Os | Quartus |
| Stratix-II GX EP2SGX90-3 |
3182 | 6 M4Ks | 11296 | - | - | 7.2 |