- Compliant with PCI Express Base Specification 1.1
- Implements Transaction, Data Link, and Physical protocol layers in hardware
- Supports x1 and x4 link widths
- Offers a data rate of 2.5 Gbps per lane
- Supports up to eight Virtual Channels
- Supports lane reversal and polarity inversion
- PCI Configuration space type 0 header
- MSI capability support
- End-to-end cyclic redundancy code (ECRC) generation and checking support
- Advanced Error Reporting capability support
- Configurable TLP data payload size, from 128B to 4kB
- Configurable size for the Transmit Retry and Receive data buffers
- Modular architecture
- Synchronous design
- 64-bit internal datapath at 125MHz •
- Application Interface (AIF) for easier system integration using industry standard bus interfaces (e.g., Wishbone, AMBA™); handles up to 8 DMA channels
- Conforms to standard PIPE interface for compatibility with any 16-bit PIPE-compliant PHY
Call or click.
- CPXP-EPx8 PCI Express Endpoint Controller Core with SoC Bridge Extensions for AMBA™ AXI
- PCIEXPAIF Application Interface Core for Altera and Xilinx FPGA PCIe Hard IP
The core is designed to work with any 16-bit PIPE-compliant
physical layer (PHY). Internal testing and customer experiences
have verified this with PHYs from several sources, including:
Altera, ARM, Genesys Logic, Jmicron, NXP, Snowbush, and Xilinx.
PCIe Development Boards
We conduct physical inter-operability testing with systems and boards from a variety of trusted vendors, including Agilent, Altera, Dini Group, Hardi (now Synplicity) and Genesys Logic.
PCIe Chipset Interoperability
While the core is rigorously designed to conform to the
specification, we verify this through real-world testing
with popular host chipsets, including:
• Intel I915
• Intel I945
• Intel I965
• Intel I975
• nVidia nForce 430
• nVidia nForce 550
• nVidia nForce 570 SLI
• nVidia nForce 590 SLI
• nVidia MPC55 Tritium
• nVidia MPC61
• nVidia C55 Tritium
• VIA PT890Pro
• SIS 986
• SIS 671FX
Avoiding unexpected challenges in PCI Express core integration, April, 2006, Embedded Computing Design
Download our DATE 06 slides: PCI Express Core Integration with the OCP Bus
CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone Core
Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It is available to act as a bridge to standard buses including AMBA™ AHB, AMBA™ AXI and Wishbone.
The scalable and flexible core has a modular architecture and a high-performance, low-latency design. It supports multiple device link widths to better match the bandwidth needs of specific applications—x1 (single lane) and x4 (four lane)—and offers bi-directional data rates from 250MB/s (x1) to 1GB/s (x4). It supports most advanced PCI Express capabilities, including message signaled interrupts, multiple virtual channels, advanced error reporting, end-to-end cyclic redundancy check, and power management features. Multi-lane versions of the core support lane reversal and polarity inversion.
The core has an Application Interface (AIF) layer that makes integration
significantly easier by relieving the designer from the complexity of
transaction layer packet (TLP) handling. This AIF includes a DMA controller
and handles the TLP encoding and decoding, and provides an interface to
popular system buses, including Wishbone and AMBA™ AHB, AXI, and AXI4.
The external connection interface from the core conforms to the Intel® PIPE specification, ensuring compatibility with any 16-bit PIPE-compliant physical layer (PHY). The core has been successfully used with PHYs from multiple vendors.
The synchronous, latch-free core design was rigorously verified for compliance with the PCI Express specification. The core has been tested for interoperability with multiple motherboards using chipsets from various vendors, and is in use by multiple customers.
See representative implementation results (each in a new pop-up window):
PCI Express is rapidly being adopted for a variety of interconnection applications, including:
- Network servers
- Graphics and multimedia
- Communications and mobile product
- Industrial, automotive, and other embedded systems
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified using Avery's PCI-Xactor verification tool. Interoperability has been verified with Intel, nVidia, VIA, and SIS chipsets, and PHYs from GeneSys Logic, Altera, and XIlinx have been successfully used. The core is in use by multiple customers.
The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:
- ASIC cores: HDL RTL source of the CPXP-EP and CPXP-EP-AIF
FPGA cores: Post-synthesis EDIF netlist of the CPXP-EP and CPXP-EP-AIF
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis or place and route script
- Comprehensive user documentation