The following sample results from 1 and 4 link widths implementations of the core are shown below (at the required frequency of 125 MHz, with a single VC, no ECRC, max. payload 256B, 2kB Retry buffer and 4kB Receive buffer). Actual slice count dependent on percentage of unrelated logic – see Mapping Report File for details. Only PCI Express bus interface signals are routed off-chip for reported IOB.
| Xilinx Devices | Link Width | Slices | IOB | BRAM | CMT/GTx | ISE version |
| Virtex-4 4VLX100-12 |
x1 | 5,545 | 7 | 4 | - | 10.1i |
| Virtex-4 4VLX100-12 |
x4 | 7,922 | 19 | 4 | - | 10.1i |
| Virtex-5 5VLX50T-1 |
x1 | 2,964 | 7 | 4 | 1/1 | 12.1i |
| Virtex-5 5VLX50T-1 |
x4 | 3,471 | 19 | 4 | 1/4 | 12.1i |
| Virtex-6 6VLX75T-1 |
x1 | 2,278 | 7 | 4 | 0/1 | 12.1i |
| Virtex-6 6VLX75T-1 |
x4 | 3,321 | 19 | 4 | 0/4 | 12.1i |
| Spartan-6 6SLX75T-4 |
x1 | 2,451 | 7 | 4 | 1/1 | 12.1i |
| Spartan-6 6SLX75T-4 |
x4 | 3,393 | 19 | 4 | 1/4 | 12.1i |