The following sample results were obtained at the required frequency of 125 MHz, and with a single Virtual Channel (VC0), Maximum Payload of 256B, a 4kB Retry buffer, a 4kB Receive buffer, no ECRC, and using a generic Application Interface.
| Link Width | Technology | Approx. Area |
| x1 | TSMC 0.13 µm | 45,300 gates |
| x1 | TSMC 0.18µm | 45,100 gates |
| x1 | TSMC 90 nm | 41,000 gates |
| x4 | TSMC 0.13 µm | 59,300 gates |
| x4 | TSMC 0.18 µm | 58,700 gates |
| x4 | TSMC 90 nm | 53,800 gates |
The core includes an Application Interface (AIF) extension, an additional subsystem for that may be used to integrate the core with SoC designs using custom or various standard interfaces. The sample implementation results shown below show the additional gates needed for a Wishbone AIF with two and eight DMA channels.
| DMA Channels | Technology | Approx. Area |
| 2 | TSMC 0.13 µm | 24,400 gates |
| 2 | TSMC 0.18µm | 23,800 gates |
| 2 | TSMC 90 nm | 21,900 gates |
| 8 | TSMC 0.13 µm | 53,000 gates |
| 8 | TSMC 0.18 µm | 52,400 gates |
| 8 | TSMC 90 nm | 47,000 gates |