The results from 1 and 4 link widths implementations of the core are shown below (at the required frequency of 125 MHz, with a single VC, no ECRC, max. payload 256B, two 64-bit BARs, 2kB Retry buffer and 32kB Receive buffer). Only PCI Express bus interface signals are routed off-chip
| Supported Family | Link Width | ALUTs | IOBs | Memory (bits) | GXB | PLL | Tool Version |
| Stratix II GX 2SGX90-3 | x1 | 8,371 | 7 | 49,408 | 1 | 1 | 6.0 SP1 |
| Stratix II GX 2SGX90-3 | x4 | 10,816 | 19 | 49,408 | 4 | 1 | 6.0 SP1 |
| Arria GX 1AGX60-6 | x1 | 7,545 | 7 | 49,408 | 1 | 1 | 7.1 SP1 |
| Arria GX 1AGX60-6 | x4 | 10,401 | 19 | 49,408 | 4 | 1 | 7.1 SP1 |