Pre-layout results after area optimization during synthesis, as reported from the synthesis tool and silicon vendor design kit under typical conditions, while all core I/Os are assumed to be routed on-chip.
| ASIC Technology |
Logic Eq. Gates |
Frequency |
Memory |
UMC 0.18µ process |
24,262 |
250 MHz |
960 bits |
TSMC 0.09µ process |
26,464 |
450 MHz |
960 bits |