All core I/Os assumed to be routed on-chip, with pre-layout results after area optimization during synthesis, as reported from synthesis tool and silicon vendor design kit under typical conditions.
| ASIC Technology |
Logic Eq. Gates |
Frequency |
Memory |
UMC 0.18µ process |
25,657 |
250 MHz |
960 bits |
TSMC 0.09µ process |
23,757 |
450 MHz |
960 bits |