All core I/Os are assumed to be routed on-chip and with pre-layout results after area optimization during synthesis, as reported from the synthesis tool and silicon vendor design kit under typical conditions.
| ASIC Technology | Logic Eq. Gates |
Frequency |
Memory |
| UMC 0.18µ process | 31,593 |
250 MHz |
960 bits |
| TSMC 0.09µ process | 30,383 |
450 MHz |
960 bits |