CSC IP Core CSC Color Space Conversion Core

The CSC core is a compact, high-performance, highly flexible color space conversion core, which can be used to convert from any color space with 3 color channels, to any color space with 3 color channels (e.g. RGB to YCrCb, YCrCb to RGB).

Different color space models are used for different purposes in video/image processing systems. For example computer monitors typically receive frames in the RGB color space, while in order to be compressed frames are typically converted to a luminance – chrominance color space (e.g. YCrCb). So, color space conversion is often necessary when transferring data between devices that use different color space models.

The CSC is a small, fast design that implements a single conversion function. Two other CSC family cores are also available:

• The CSC-P Programmable version can convert from any color space with three color channels to any other color space with three color channels (download CSC-P PDF datasheet). It processes all three channels in parallel.
• The CSC-PT Programmable, Time-Multiplexed IO version can also handle any color space conversion, but it multiplexes the three color channels on a single bus (download the CSC-PT PDF datasheet). The CSC-PT is thus smaller, but the CSC-P has three times the throughput of the CSC-PT.

The CSC cores area testable, microcode-free designs developed for reuse in ASICs and FPGAs.

 

The provided indicative implementation data are acquired for the pipelined version of the core implementing Y’CrCb to computer R’G’B’ conversion with input and output bit-width of 8 bits, conversion coefficients bit-width of 10 bits, and the data-path accuracy of 12 bits. Other conversions perform slightly faster, and occupy approximately the same area.

It is noted that area requirements are reduced for the non-pipelined version of the core, and if the enable and clear ports are not used (i.e. they are hardwired before synthesis). For example, for the same configuration described above but with hardwiring the enable and clear ports, the core occupies 22% less area (4157 eq. gates).

See representative implementation results (each in a new pop-up window):

CSC

CSC-P Non-Pipelined

CSC-P Pipelined

CSC-PT Non-Pipelined

CSC-PT Pipelined

Applications

The CSC can be utilized for a variety of multimedia applications including:

• Image Grabbers
• Display Systems
• Image/Video processing applications
• Image/Video compression / decompression systems
  

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• An example chip implementation, which uses the CSC in a sample system
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide