CAST CSC-PT Pipelined Core ASIC Implementation Results

The following indicative implementation data are acquired after setting the Input and output bit-width to 8 bits, the conversion coefficients bit-width to 10 bits, and the data-path accuracy to 12 bit.

ASIC Technology

Logic Gates

I/O

fMAX (MHz)
HCLK/CCLK/PCLK

Memory

Pipelined

ATMEL
0.18 um

6,099

39

159

-

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