CAST SPI-MEM-CTRL Core — XILINX FPGA Results

The following are indicative Xilinx implementation results, for which all internal FIFOs are implemented with available SRAM resources.

Xilinx Devices Slices Fmax (MHz)
core_clk/spi_sclk		 Special Features
Spartan-6
6SLX9-3		 718 120 / 56 4 BRAMs
Virtex-5
5VLX30-3		 872 175 / 91 4 BRAMs
Virtex-6
6VLX75T-3		 657 225 / 98 4 BRAMs

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