Device Independent
- Automatic identification of a variety of memories
- Configurable memory features to allow support of more serial flash devices
Efficient Bandwidth Utilization
- Automatic identification of maximum bandwidth access mode among:
- single SPI
- dual output SPI
- dual input / output SPI
- quad input / output SPI
Flexible Access Model
- Registered Mapped I/O
- Host issues access request, reads and writes data via registers access
- Read access sizes from 1 byte up to memory density
- Read accesses starting from any address offset
- Write access sizes from 4 bytes up to memory density
- Write accesses starting from any address offset that is multiple of 4
- Erasure of:
- any sector (4KB)
- any block (64KB)
- whole chip
Ease of Integration
- Auto-detection of a wide set of serial flash devices to minimize programming overhead
- Auto detection of the fastest way to read or program the memory, to maximize bandwidth and minimize programming overhead
- Deep Power-down Mode support to minimize power consumption
- Optional AXI-4 interface . Other interfaces available on request.
Design Quality
- Robust verification with integrated testbench environment.
-
Scan-ready design
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PDF Datasheets
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Options for this Core
SPI-MEM-AXI an AMBA/AXI-4 Interface for the Serial Flash Controller Core
Memory IP Core SPI-MEM-CTRLSerial Flash Memory Controller Core
The SPI-MEM-CTRL core offers the interconnection between a host and a serial NOR-flash memory using the Serial Peripheral Interface. The SPI-MEM-CTRL supports Single, Dual Input, Dual Input/Output and Quad Input/Output SPI accesses.
The core automatically identifies a variety of serial flash memories and communicates with the attached device at the maximum possible bandwidth. Register accesses are used to insert access requests and read/write data into/out SPI-MEM-CTRL core. Communication with devices other than those automatically identified, is also feasible as the core can be programmed with the memory device parameters. The SPI-MEM-CTRL can read, write or erase any part of the memory.
The core is rigorously verified. A complete verification environment that helps designers verifies the functioning and compliance of the core, and additional aids for system-level simulation are available.
See representative implementation results (each in a new pop-up window):
Applications
The core’s flexibility, performance, and simplicity of use make it an excellent memory controller for nearly any application using the targeted SDRAM and DIMM devices.
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The SPI-MEM-CTRL core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Software (C++) Vector Generator
- Sophisticated HDL Testbench
- Simulation script, vectors and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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