SFLASH-AHB Core — ASIC Implementation Results

The SFLASH-AHB can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.




Clock Freq.  (MHz)

XIP on, DMA off, Auto-config. off

TSMC 16nm

(sc7, svt, c16)

11,500 eq. Gates

AHB Clock 1,000

Serial Clock 167

XIP on, DMA on, Auto-config. on

18,000 eq. Gates


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