Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

MIPI
SPMI Master/Slave

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

SPI NOR- and NAND-Flash controller supporting XIP and STR or DTR over single, dual, quad, twin-quad, and octal SPI links.

Flexible Flash Access Modes

  • XIP - Allows AHB bus masters to read directly from the flash with zero software overhead.
  • DMA – Optional DMA engine can be programmed to transfer data from/to system to/from the Flash device
  • Boot-Image Copy -  After reset the core uses its
  • DMA engine to autonomously copy an amount of data from Flash to the AHB address space
  • Slave Mode – System accesses core registers to transfer data to/from the Flash

Easy Integration & Operation

  • Flash Device-independent. The flash device parameters can be set in the following ways:
    • Automatically after reset. A list of automatically identifiable devices is provided to the core in an external memory
    • At run time via configuration registers programming
    • At synthesis time. Verilog defines for reset values of all configuration registers
  • Zero software overhead with XIP and optional auto-configuration
  • 32-bit and 64-bit AHB bus interfaces. Data-bus widths are configurable at synthesis time
  • Configurable SPI interface:
    • Single, Dual, Twin-Quad and Octal SPI

    • Single Transfer Rate (STR) or Dual Transfer Rate (DTR)
    • 4, 8, 16, or 32 bit word transmissions per data line
    • Full and Half Duplex operation
    • Configurable number of slaves (Chip-Select lines)
    • Programmable serial clock polarity and phase

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • PFLASH-CTRL Parallel NOR Flash Controller IP Core
  • OSPI-XIP-AHB Single, Dual, Quad, & Octal SPI Flash Controller for AHB
  • QSPI-XIP-AHB Quad SPI Bus Controller with XIP, for AHB
  • QSPI-XIP-AXI Quad SPI Bus Controller with XIP, for AXI
  • QSPI-APB Quad-Bit Serial Peripheral Interface Master/Slave
  • SPI-APB Serial Peripheral Interface Master/Slave

SFLASH-AHB Single, Dual, Quad, and Octal SPI Flash Controller with XIP & DMA, for AHB

The SFLASH-AHB core is a versatile SPI flash memory controller. It allows a system to easily access an SPI flash device or directly boot from it.

The core allows the system to interface with one or more serial flash devices in one of the following modes: a) in Slave mode by accessing its registers via an AHB slave interface, b) in DMA mode where the system programs the internal DMA engine, and then the core accordingly drives its AHB master interface, c) in eXecute In-Place (XIP) mode where the core allows the system to directly access the SPI memory address space via an AHB slave interface, d) in Boot-Image copy mode where after reset the core will autonomously copy an amount of data (boot-image) from the SPI memory to the AHB address space (e.g. on a shadow RAM) using its AHB master interface.

The core can work with single, dual, quad, twin-quad, and octal SPI flash devices. To enable use with flash devices from different vendors, the core offers two ways of configuring the device-specific parameters: a) via registers, where the system is responsible to identify the connected flash device and program the appropriate values to the core's registers and b) by using the auto-configuration feature, where the core will autonomously identify the connected flash device and program itself accordingly. The auto-configuration functionality uses a user-provided memory that stores a list of automatically identifiable devices along with their features.

The SFLASH-AHB can be easily configured to match different application requirements. Data and address width of the AHB interfaces, instantiation of the DMA engine and the auto-configuration logic, maximum number of Flash devices that the core supports, and reset values for all configuration registers, are some of the design parameters that can be controlled by means of simple Verilog defines.

This core has been designed with industry best practices. It is LINT-clean and scan ready, it has been verified through rigorous verification, and it is silicon-proven.

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Block Diagram

SFLASH-AHB block diagram

Size and Performance

The SFLASH-AHB can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample implementation data. Please contact CAST to get characterization data for your target configuration and technology.

Deliverables

 

Comparing SPI Cores Family

Core Name
Features
SPI Mode
SPI
Master
SPI
Slave
DTR
XIP
Auto
Config
Auto
Boot
DMA
I/F to ext
DMA
Host
Interface
SFLASH-AHB 1x, 2x, 4x, 8x supported not supported supported supported, but may be removed supported, but may be removed supported, but may be removed supported, but may be removed not supported AHB 32b/64b
SPI-APB
1x
supported
supported
not supported
not supported
not supported not supported not supported
not supported
APB 32b
QSPI-APB
1x, 2x, 4x
supported
supported
not supported
not supported
not supported not supported not supported
supported
APB 32b
QSPI-XIP-AHB
1x, 2x, 4x
supported
supported
not supported
supported, but may be removed
not supported not supported not supported
supported
AHB 32b
QSPI-XIP-AXI
1x, 2x, 4x
supported
supported
not supported
supported, but may be removed
not supported not supported not supported
supported
AXI 32b
OSPI-XIP-AHB
1x, 2x, 4x, 8x
supported
not supported
supported
supported
not supported not supported not supported
supported
AHB 32b

     supported, but may be removed Feature supported, but can optionally be removed
     supported Feature supported
     not supported Feature not supported
     DTR: Dual Transfer Rate
     XIP: Execute in place

 

 

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