The following are sample ASIC pre-layout results, as reported from the synthesis tool and silicon vendor design kit under worst conditions. This is for a full-featured controller supporting two chip selects, with all core I/Os assumed to be routed on-chip.
| ASIC Technology | Logic Eq. Gates (excl. routing) |
Frequency |
| UMC 0.18µ process | 9,400 | >> 200 MHz |
| TSMC 0.09µ process | 8,400 | >> 200 MHz |
Note that the controller core can achieve operating frequencies in excess of 200 MHz with some technologies. However careful clock distribution is essential to support SDRAM devices operating at frequencies higher than 100 Mhz. The use of a PLL and/or a clock delay line is required in most cases in order to achieve maximum SDRAM frequencies.