- Interfaces directly to Mobile and ordinary Single Data Rate (SDR) SDRAM chips and registered/unbuffered DIMMS
- Supports address space up to 2G (230 words) and
- one to eight chip selects,
- two to four banks,
- eleven to fourteen row bits,
- eight to twelve column bits
- Manages up to four 2GB DIMMs
- Automatically generates initialization and refresh sequences
- Efficient bank management and access cascading for up to 100% memory throughput utilization
- Programmable automatic refresh policy reduces refresh overhead
- Runtime-configurable features for application flexibility
- timing parameters: CAS latency, tRP, tRCD, tREFC, tMRD, etc.
- memory settings: Row bits, Column bits, Bank bits, number of CSs
- Mobile-SDR support and Extended-Mode-Register (EMR) values
- Bank status monitoring means banks are opened or closed only when necessary, minimizing access delays
- Configurable auto-close mechanism minimizes power dissipation by precharging inactive banks
- Configurable auto power-down and auto-self-refresh: SDR devices put in power-down mode after some time of inactivity, and in self-refresh mode after a further time of inactivity.
- Energy-saving sleep-mode: after setting SDRAM devices in self-refresh mode, core “turns off” most of the internal circuitry to minimize power dissipation
- Flexible user-interface: separate read and write interfaces support from single to any arbitrary length burst accesses; access lengths defined using an access-size bus and/or a burst-stop signal.
- Easily interfaced to legacy on-chip synchronous microprocessor buses that support burst-accesses and handshaking, or to on-chip FIFOs (respective wrappers available on request)
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Memory IP Core SDR-SDRAM-CTRL Single Data Rate Mobile SDRAM Controller Core
Implements a controller providing a simple, flexible, burst-optimized interface to all industry-standard single data rate (SDR) Mobile and ordinary SDRAM memory devices. Also works with registered/unbuffered DIMMs. It supports up to a 2G (230 word) memory address space, provides up to eight chip selects, and manages up to four memory banks.
The core automatically handles memory management, initialization, and refresh operations. It gives the user a simple command interface, hiding details of the required address, page, and burst handling procedures. All memory parameters are runtime-configurable, including timing (CAS Latency, tRP, etc.), memory setting (Row Bits, Column Bits, etc.), and Mobile-SD and Extended-Mode-Register settings. A configurable auto-close mechanism precharges inactive memory banks to minimize power dissipation, and configurable power-down and self-refresh features plus support for sleep mode help reduce power consumption.
The flexible user interface features separate read and write ports, and the core handles single word accesses as well as arbitrary-length bursts, emulating a linear memory space with no page or bank boundaries. A pipelined design achieves maximum memory bandwidth utilization, while parallel state machine design practices further improve performance. The rigorously-verified core is silicon-proven and has been embedded in several products. It offers very competitive implementation characteristics, requiring for example just 9,400 gates and running at 200 MHz in a typical .18 micron ASIC process.
See representative implementation results (each in a new pop-up window):
Applications
The core’s flexibility, performance, and simplicity of use make it an excellent memory controller for nearly any application using the targeted SDRAM and DIMM devices.
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation, rigorous code coverage measurements, and FPGA prototyping.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) and vector generation application
- A collection of tests executed directly by the Testbench
- Simulation script, vectors and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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