CAST SDIO-HOST Core — XILINX FPGA Results

The following are sample Xilinx results for the core configured with, FIFO buffer size of 2 * 2kB, a 32-bit Generic interface, memories, and no CPRM.

Family	Slice	BRAM	Fmax (MHz)	Config
Virrtex5 xc5vfx70t-3	1508	1 RAM36K	208	No DMA, 1 Slot,
Virtex6 xc5vfx70t-3	1281	1 RAMB36E1	208
Spartan6 xc6slx100t-4	1399	2 RAMB16BW	100
Virrtex5 xc5vfx70t-3	1784	1 RAM36K	208	Simple DMA, 1 Slot,
Virtex6 xc5vfx70t-3	1623	1 RAMB36E1	208
Spartan6 xc6slx100t-4	1617	2 RAMB16BW	100
Virrtex5 xc5vfx70t-3	2210	1 RAM36K	208	Advanced DMA, 1 Slot
Virtex6 xc5vfx70t-3	2020	1 RAMB36E1	208
Spartan6 xc6slx100t-4	2223	2 RAMB16BW	100
Virrtex5 xc5vfx70t-3	3918	1 RAM36K	208	Advanced DMA, 4 Slots
Virtex6 xc5vfx70t-3	3468	1 RAMB36E1	208
Spartan6 xc6slx100t-4	3764	2 RAMB16BW	100