Sample ASIC results for the core optimized with a clock constraint of 100 MHz.
ASIC Technology |
Area | Fmax |
| TSMC 65 nm (Full Core Configuration) |
120,267 gates | 100 MHz |
TSMC 90 nm |
51,758 gates | 100 MHz |
| TSMC 130 nm (4 devices per bank, BCH 8 and DMA) |
53,824 gates | 100 MHz |
| TSMC 180 nm (4 devices per bank, BCH 8 and DMA) |
47,683 gates | 100 MHz |
| TSMC 40 nm G (8 devices per bank, BCH 8, ClearNAND, and DMA) |
52,955 gates | 100 MHz |