Why buy this core?
- Implements critical functions in hardware to off-load the system processor and increase throughput.
- Configurablity enables the smallest area and lowest price for each specific memory application.
- Designed for very high performance; SSD-ready.
- Available hardware development platform facilitates system design and verification.
- Silicon-proven, sixth-generation IP from an experienced team reduces your development risk.
- DDR2-SDRAM-CTRL DDR/DDR2 SDRAM Memory Controller
- SDIO-HOST SD/SDIO/MMC/e-MMC Card Host Controller
- SDR-SDRAM-CTRL Single Data Rate Mobile SDRAM Controller
- SPI-MEM-CTRL Serial Flash Memory Controller
11/15/2011 CAST NAND Flash Controller Supports Latest High-Speed Memories and is Ready for ONFI 3
5/11/2011 NAND Flash Memory Controller IP Core from CAST now Faster and Easier to Integrate
Learn more about NAND Flash at Wikipedia.
Visit the Open NAND Flash Interface Working Group (ONFI) site.
Peruse a useful collection of NAND Flash Application Notes at Data I/O's site.
Memory IP Core NANDFLASH-CTRL NAND Flash Memory Controller IP Core
- ONFI 3.0.
Call for details:
The full-featured core efficiently manages the read/write interactions between a master host system and Single- or Multi-Level Cell (SLC or MLC) NAND flash memory devices. The core includes an optional direct memory access (DMA) manager, uses a comprehensive command set for easy NAND Flash memory access, automatically remaps corrupted memory blocks to improve reliability, can protect memory areas against writes with a block lock mode, has built-in power-saving features, and can boot software directly from Flash memory.
The controller works with any suitable memory device with 512 Bytes to 32-kB page sizes supporting the Open NAND Flash Interface Working Group (ONFI) standards.
The NAND Flash Controller employs a standard OCP 2.0 socket interface to facilitate easy adaption into all types of design structures depending on the designer needs. OCP is being widely adopted due to its ease of integration and flexibility. Wrappers supporting AMBA 2 AHB, OPB/PLB, Avalon and FlexBus buses are available and other structures are available by request.
The Controller offers two error code correction (ECC) mechanisms from the relatively simple single-bit Hamming Code to more sophisticated high-speed BCH (Bose, Ray-Chaudhuri and Hocquenghem) ECC. BCH targets applications with high-density memory as well as direct boot from the NAND flash device.
This sixth-generation product builds on silicon-proven previous versions of the controller. Developed for reuse in ASICs and FPGAs, the core is fully synchronous with positive-edge clocking, has no internal three-state buses, and uses a synchronous reset so scan insertion is straightforward. The included verification package features bus models for the AHB master and NAND flash devices to help designers verify the functioning of the core.
- Support for High Speed NAND Flash memories (up to 200MB/s)
- Command interface conforms to ONFI Standard 1.x & 2.2 for compatibility with major manufacturers (e.g., Micron, Numonyx)
- Support for popular standard memory device manufacturers (e.g. Samsung, Toshiba, etc.)
- Supports Single- and Multi-Level Cell (SLC and MLC) flash devices
- Supports ClearNAND and Toggle Mode DDR NAND flash devices
- Two options for ECC:
- Simple Hamming-Code mechanism (for SLC devices)
- Sophisticated BCH multiple-bit mechanism (for MLC devices) correcting up to 32 bits
- Supports page sizes from 512 Bytes to 32 kB
- OCP 2.0 socket interface for easy integration with any system bus
- Available system interfaces wrapper supports:
- AMBA™ AHB
- Custom development of system bus wrappers
- Configurable number of memory banks and devices per bank
- Define number of chip select, ready/busy, and write protect signals
- Allows different memory type for each bank
- Enables booting from flash, with configurable boot sequence
- Adapts to a variety of system and memory types, with configurable (via special function registers):
- timing parameters
- 4/5 address cycles
- ECC calculation turn on/off
- Write/Erase Protection size
- Interrupt enable/disable
- Built-in optional Direct Memory Access (DMA) manager to speed data transfer and off-load the host
- Synchronous (DDR mode) and asynchronous interfaces
- Bad Block management supports Automatic Write/Read Page (with data correction)
- Extended Power Save Mode for low-power applications
- Optional support for the Write/Erase Protection
- Easily adjustable generic parameters
- Number of device banks
- Endian Type (Big or Little)
- Custom NAND Flash Controller Driver available; allows designer to develop system software without detailed NAND flash controller knowledge
The core is suitable for controlling embedded storage (e.g. in mobile devices, network routers, and point-of-sale systems) and solid state device (SSD) mass storage for USB flash drives, digital cameras, laptops, and more.
- Written in “C”
- Contains functions which support common memory functions
- Contains functions which support custom memory features of Micron, Samsung and ST devices
- DMA support module configures DMA and transmits data
- Configurable to reduce resource requirements
- Hardware mapping of memory blocks
- See associated datasheet
The NANDFLASH-CTRL core is partitioned into modules and comes with external elements as shown in the block diagram and described below.
The Design Control Unit controls all other modules based on the SFR values and current controller state. The main tasks of this module are:
- Provide enable/disable signal to the DMA and SIU units when they try to get access the FIFO module. Only one of the two units can be active at time.
- Enable/Disable the ECC module.
- Provide control signals to the NCU unit
- Execute the boot sequence
- Interrupt controller
Opens a window in the address space where the BUFFER and all SFRs are visible, providing access to these elements. Works as glue logic between the system interface and internal controller bus, coordinating their interaction. It is responsible for generating the internal request signal if the controller buffer must be read directly using the controller interface, and it holds transmission on the external bus if access can’t be granted.
Speeds up data transfer between a device on the system bus and the memory, and decreases system bus burden.
A 32-bit width asynchronous FIFO module which facilitates transferring data between the input module and NCU when the command sequence is executed.
The NAND Control Unit is responsible for generation of the NAND flash device access sequences. The unit uses the control signals provided by the DCU. In some configurations it can be multiple instantiated to allow parallel access to multiple NAND flash devices. The NCU uses our proprietary interface to the PHY Interface unit.
This is an error correction code calculator and a correction unit. A correction word is calculated for each 512B sub page of the NAND Flash memory page. During the read operation the unit can automatically correct bad bits without any interaction with the external system. It has a status register, the bits of which signal errors occurring during a read, and then inform if errors were corrected. It is possible to choose between a simpler unit that can correct only one error per 512B sub page and a more advanced unit that can correct multiple errors. The choice depends on the NAND Flash memory type that is in use. Depending on the end-user application, it is possible to choose between two solutions. The first one is based on the Hamming algorithm that allows correction of one error for each 512B sub page, which is a good choice for SLC memories. The other solution uses the BCH algorithms and is more efficient if MLC memories are used. The ECC module has an integrated FIFO that is used to transfer the calculated words to the NCU modules during the encode process, and to store the calculated partial syndromes during the decode process.
This module provides the DDR data interface for the new High Speed devices.
For this USB thumb drive, the core is implemented with an internal buffer and tri-state buffers. Data goes through a USB controller, and a microcontroller manages data flow, sets parameters of data transmission for NANDFLASH-CTRL, controls the USB, and handles all aspects connected with a File System implemented in this storage device.
The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email tech-nical support are included, starting with the first interac-tion. Additional maintenance and support options are available.
Extensive verification has been performed, using code coverage tests, simulation with multiple tools, and implementation and testing in an FPGA demonstration system.
Verification has been performed with many different devices from Micron, Samsung, STM and Toshiba.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- VHDL or Verilog source code for the core
- An example design that uses the core and illustrates how to build and connect memory and tri-state buffers
- Sophisticated HDL Test Bench that instantiates the example design and related elements
- Interface wrappers when ordered
- Simulation script, vectors, expected results, and comparison utility
- Synthesis scripts
- Comprehensive user documentation, including detailed specifications and a system integration guide
NAND Flash Controller Driver – a low-level software driver that represents a first abstraction layer of the core to relieve the higher level application layer from hardware management.
Critical functions this controller implements in hardware:
- Bad Block Management
- AES 256
- multiple command functions
Configurable featues include:
- ECC correction strength
- system bus
- block size
- boot mode
- page remapping
- write protect
- asynchronous or source synchronous
All built on our decade of experience with our congifurable 8051 cores.
Special high-performance featues include:
- super sequencer
- high ECC strength
- large page size
Works with the Marvell PXA300 development board from HiTech Global.
We've been providing NAND FLash Controller IP cores—and helping customers succeed with them—since 2006.
This version is built on four previous generations of NAND FLash controller IP. It is hardware verified and silicon proven.
Customers range from established Tier 1 firms to brand new start-ups; contct Sales for references.
Our experience lets us also offer you IP integration design services, customer software driver expertise, and more, to help you complete yuor project on-time and on-budget.