Memory IP Core DDR2-SDRAM-CTRL DDR/DDR2 SDRAM Memory Controller Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

The DDR2-SDRAM-CTRL core provides a simplified, pipelined, burst-optimized interface to all industry-standard DDR and DDR-II SDRAM devices currently available, including Mobile DDR SDRAMs. It features:

• Simplicity. All required management, initialization, address and burst handling procedures are done by the core. The control, write-data, and read-data paths are split, enabling higher performance and easier integration.
• Performance. The core achieves maximum bandwidth utilization through pipelined and parallel architectural design practices.
• Flexibility. All memory parameters (timing parameters, memory size parameters, mobile-DDR support, auto-refresh policies, etc.) are runtime configurable.
• Easier Integration. Most necessary related components—DDR/DDR-II Controller, data-path FIFOs, DLLs—come built into the core, and some FPGA versions even include a PHY.

The core has been carefully designed and rigorously verified, and is delivered with comprehensive documentation and a complete verification environment.

See representative implementation results (each in a new pop-up window):

Features

• Interfaces to all industry standard DDR and DDR-II SDRAM DIMMs and chips, including Mobile DDR SDRAMs.
• High-performance architecture, with a three-stage processing queue for maximum bandwidth utilization.
• Pipelined design facilitates integration and enables high clock rates.
• Includes power-down and self-refresh, critical for low-power applications.
• Datapath logic with small FIFOs, enables handshaking mechanism for enhanced performance and easier integration.
• Two different PHY implementations available: an advanced delayed-DQS capture mechanism with per-bit deskew, and a delayed-clock capture with dual-port synchronizing FIFO.
• Utilizes per-bank status monitoring.
• Incorporates a programmable auto-precharge mechanism.
• Incorporates a programmable automatic refresh policy.
• Supports up to eight chip-selects, up to eight banks per chip, twelve to fifteen row bits, and nine to twelve columns bits.
• Runtime-configurable parameters ensure flexibility: eleven timing parameters, CAS latency, Burst Length, Row bits, Column bits, Bank bits, number of CSs, Extended-Mode-Registers’ values, registered-DIMM support, power-saving and auto-precharge mechanism activation.
• Flexible user-interface, with split command, write-data and read-data paths. All paths support hand-shaking mechanisms.
• Multi-burst access support: access requests can have any size burst lengths from 1 to 65536; the core segments these into an appropriate number of SDRAM bursts.

Applications

Any application requiring efficient, high performance access to DDR / DDR-II SDRAM memory, including:

• Processor Interfaces
• Networking
• Video / Image Processing
  

Block Diagram

 

Functional Description

After power-up the SDRAM device(s) are initialized and then physical-layer calibration commences. After the calibration phase is complete the controller is ready to serve read and write requests.

Requests are served in a pipelined mode, that is, while a request is in progress, another request can be issued. Write and read data are conveyed/received to/from the controller via separate interfaces with distinct handshaking signals.

The DDR2-SDRAM-CTRL core incorporates a parallel auto-close mechanism, which precharges active SDRAM banks that are currently inactive. It also incorporates an Auto-Power-Down & Auto-Self-Refresh mechanism which sets the SDRAM device into “power-down” mode after a configurable time of inactivity. When in power-down mode and if a user or auto-refresh request is received, the SDRAM is set back into normal-mode and the request is served. If an additional time of inactivity is observed, the SDRAM device(s) are set into self-refresh mode, during which the internal SDRAM self-refresh mechanism is used. During this mode, most of the internal circuitry is “frozen”, dropping power dissipation to a minimum. And finally, it also takes care of SDRAM refresh requirements.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. It has also been proven in FPGA prototyping boards.

Deliverables

The core is available in FPGA (netlist) forms, and includes everything required for successful implementation:

• Post-synthesis EDIF netlist
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
• Simulation script, vectors, and expected results
• Vector generation Software
• Place and route script
• Comprehensive user documentation, including detailed specifications and a system integration guide

 

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx

 

  This core developed by the memory experts at Alma Technologies S.A.