The following sample results are obtained after speed optimization during synthesis and place and route, while assuming that only SDRAM I/Os are routed off-chip and a 16-bit wide SDRAM data bus.
| Xilinx Devices | Slices |
Frequency | I/O | BRAM | Special Features |
ISE |
| Spartan-3E 3S1200E-5 |
1,279 | 148 MHz | 48 | - | 1 DCM | 8.2.03i |
| Virtex-II Pro 2VP4-7 |
1,254 | 222 MHz | 48 | - | 1 DCM | 8.2.03i |
| Virtex-4 4VLX15-12 |
1,152 | 266 MHz | 48 | - | 1 DCM | 8.2.03i |
| Virtex-5 5VLX30-3 |
698 | 270 MHz | 48 | - | 1 DCM | 9.1.01i |
The following results assume no PHY with all I/Os routed on-chip and configured for 32-bit wide data buses and 32-word deep write and read data-FIFOs.
| Xilinx Devices | Slices |
Frequency | I/O | BRAM | Special Features |
ISE |
| Spartan-3E 3S1600E-5 |
1,164 | 147 MHz | 359 | - | - | 9.2.01 |
| Virtex-II 2V1000-6 |
1,081 | 192 MHz | 359 | - | - | 9.2.01 |
| Virtex-II Pro 2VP7-7 |
1,062 | 213 MHz | 359 | - | - | 9.2.01 |
| Virtex-4 4VLX25-12 |
1,085 | 266 MHz | 359 | - | 9.2.01 | |
| Virtex-5 5VLX30-3 |
580 | 278 MHz | 359 | - | - | 9.2.01 |