CAST DDR2-SDRAM-CTRL ASIC Implementation Results

The following are representative ASIC results were generated with a 32-bit wide DDR data-bus. Two memories (32x64 and 32x72) are also required for the read and write data-paths respectively. The depth of these memories can be reduced to 16 or less, depending on the required performance and data traffic profile.The actual cell area and NAND2 divider value used to derive Approximate Area are included since calculation methods for this vary.

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