Sample results are obtained after speed optimization during synthesis and place and route, without a PHY and while assuming that only SDRAM I/Os are routed off-chip.
| Altera Devices | Logic | Frequency | Special Features |
| Cyclone EP1C20-C6 |
1,629 LEs | 147MHz | 544 memory-bits |
| Cyclone-II EP2C35-C6 |
1,672 LEs | 171 MHz | 544 memory-bits |
| Stratix EP1S20-C5 |
1,746 LEs | 173 MHz | 544 memory-bits |
| Stratix-II EP2S30-C3 |
1,483 ALUTs | 262 MHz | 544 memory-bits |