- 5-bit address and 6-bit command length
- Bi-phase coding (also known as Manchester coding)
- Carrier frequency of 36 kHz as per the RC5 standard
- Fully synchronous design
- Generic parameter ACTIVE_LEVEL enables consistency with different types of IR transmitters
- Serial input data interface
- UART standard input data interface available; other interfaces available upon request (parallel, APB and others)
- Internal parameters enable fine tuning for use with different types of IR transmitters:
- specify the active level,
- specify the number of clock pulses needed to create the 38 kHz internal signal , and
- specify the size of the counter used to generate the 38 kHz internal signal
- Complex system of error codes allows easy detection of potential errors and glitches during transmission
- Serial output data interface
- Additional output data interfaces are available now: UART standard, AMBA APB
- Parallel and custom output interfaces available upon request
Infrared IP Core IR-RC5 IR Controller Encoder and Decoder Core
This pair of cores implements an Encoder and a Decoder for Consumer IR (CIR) infrared remote control signals using the popular RC5 IR protocol, originally developed by Philips. The cores are available individually or together.
The Encoder accepts data and control signals, encodes commands following the RC5 protocol, and outputs the commands to a suitable LED or photodiode transmission circuit. Following the RC5 protocol, the core transmits a five-bit address and a six-bit command. The simple serial input interface eases system integration, and a additional signals allow control of the transmission and indicate when it is complete.
The Decoder receives data from a photodiode or other infrared receiver. The core decodes the IR data and transmits a simple serial output signal. Handshaking signals give the user full control over the transmitted data. An extra output identifies repeating signals for processing efficiency.
The flexible cores are designed for easy system integration, with simple control interfaces. UART and AMBA APB interfaces are also available. The cores are available in HDL source code for ASICs or optimized netlists for FPGAs. Implementation results show them to be area-efficient, requiring for example 452 gates for the Encoder and 832 gates for the Decoder at over 300 MHz in a .13µm ASIC process.
See representative implementation results (each in a new pop-up window):
The cores are suitable for a wide variety of consumer products and other low-speed infrared control applications, including televisions, home theater systems, DVD players and recorders, and video game consoles.
The cores as delivered are warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The cores have been verified through extensive simulation and rigorous code coverage measurements.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench
- Simulation script, vectors and expected results
- Vector generation Software
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation