CAST USBSS-DEV Core — ASIC Implementation Results

The following are sample results (SuperSpeed only) configured for operation in with a 32-bit PIPE interface, 1 bi-directional control endpoint, two other endpoints, and support for a 32 KB on-chip buffer memory.

ASIC Technology
Approx.
Area
Frequency clk/pclk
TSMC 180nm
97,500 gates
100/125 MHz
TSMC 130nm
107,000 gates
100/125 MHz
TSMC 90nm
97,000 gates
100/125 MHz
TSMC 40nm
85,700 gates
100/125 MHz

 

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