CAST USBSS-DEV Core — Altera Implementation Results

Sample Altera results with one bidirectional control endpoint, two other endpoints, and 64kB on-chip buffer memory optimized for speed.

Altera Devices LEs / ALUTs Memory Bits DSP/
MULT
I/Os Fmax
(MHz)
Quartus
Arria-II GX
EP2AGX45-4
9,830 262,144 2 317 125 9.1
Cyclone-III
EP3C40-6
18,198 262,144 2 317 125 9.1
Cyclone-IV
EP4C30-6
18,198 262,144 2 317 125 9.1

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