USB IP Core USBSS-DEV USB 3.0 SuperSpeed Device Controller Core

On this page:Description | Features | Applications | Block Diagram | Functional Description | Example Application | Benefits | Support | Verification | Deliverables

This IP core implements a device controller that conforms to the USB 3.0 SuperSpeed specification. The SuperSpeed 3.0 USB enables data transfers up to 5 Gbps, while also reducing power requirements. Its use of Sync-N-Go technology reduces user wait-time, and it is backwards-compatible with USB 2.0. The core handles byte transfer autonomously, and bridges the USB interface to an OCP interface for straightforward system integration (AMBA® AHB and other system interfaces are also available). The USBSS-DEV can be readily customized and optimized for a wide range of specific system applications.

The core is developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, a synchronous reset and no internal tri-states; therefore, scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Features

• USB 3.0 Specification Rev. 1.0 compliant
• 32-bit OCP Slave interface implemented as a basic microprocessor interface
• Integrated DMA controller with a 32-bit OCP Master Interface
• USB 3.0 PIPE interface to PHY (32-bit)
  
• Control transfers supported by Endpoint 0
• Up to 15 IN and 15 OUT configurable/ programmable  endpoints
• Synchronous Single Port RAM interface for endpoint buffers
• Full Power Management capabilities (U1, U2 & U3 ) with LFPS support
• Bulk Stream support
• Backwards compatibility achieved through integration with the CAST USB 2.0 (Hi and Full-Speed) Device controller

Applications

The SuperSpeed USB 3.0 device controller core is suitable for a variety of applications, including mass storage products, audio/video systems, communication devices, digital cameras, networking, and digital media controllers.

Block Diagram

Functional Description

The USBSS-DEV core is partitioned into modules, as shown in the block diagram and described below:

Link Layer Module

This module works in the USB clock domain. The link layer’s responsibility  is to maintain the link connectivity to ensure reliable header packet exchange, as required by the USB 3.0 specification.

The link layer module builds and transmits packets. It has a header buffer included to store the header packets during the link management process.

This module also performs entry & exit sequences for low power states and initiates/detects inband reset.  

Protocol Layer Module

The Protocol layer manages communication between the host and the protocol layer. This module services SET ADDRESS request, while other requests are serviced by the software. It works in the USB clock domain.

Hi-Speed and Full-Speed Module (optional)

This component contains all necessary logic required
to handle USB 2.0 transactions. It can be connected directly with the external USB2.0 transceiver that is compatible with the UTMI Specification.

Endpoint Logic

Endpoint logic generates read/write signals for one single port synchronous RAM, which is used as an on-chip internal buffer for both IN and OUT endpoints. This module contains all endpoint registers and is responsible for the management of the internal buffers.

Synchronization Module

Cross clock domain synchronization module.

DMA

Integrated DMA controller. The DMA is used to control a data transfer between endpoint buffers (on-chip RAM) and external memory.

Special Function Registers

SFRs module contains a set of Special Function Registers which are used to control the USBSS-DEV operation.

Example Application

Here the USBSS-DEV is implemented with an internal single-port RAM. The core works as a USB peripheral device, transmitting data between the fast flash memory and PC using the SuperSpeed USB connection. USB data packets are transferred between the on-chip endpoint memory and system memory using an integrated USB protocol-aware DMA controller. The CPU controls the settings of endpoints and service interrupts.

Benefits

• Complete hardware and software solution
• High level of configurability
• Industry standard interfaces that simplify system integration
• Verilog coding style for true technology independence
• Customization to fit user needs
• Flexible licensing schemes

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core includes everything required for successful implementation:

• Verilog RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Sophisticated self-checking SystemC Testbench, including external endpoint buffers, models of interfaces, vectors for testing the core, and a sample chip-level example
• Simulation script, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script

• Comprehensive user documentation, including detailed specifications, integration manual, verification and test plan guides

 

On this page:Description | Features | Applications | Block Diagram | Functional Description | Example Application | Benefits | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx

This core is sourced from the IP experts at Evatronix SA.