The following are sample Xilinx results optimized for speed and configured for operation with IN 1 - 512 bytes single buffered and OUT 1 - 512 bytes single buffered. uP data width: 32-bit; USB data width: 16-bit; SlaveFIFO data width: 32-bit.
| Xilinx Devices | Slices | BRAM | GCLK | IOB | Fmax (MHz) (uP clock) |
Fmax (MHz) (usb clock) |
ISE |
| Spartan-3E xc3s500-5 |
2431 | 8 | 3 | 222 | 30 | 57 | 9.2.02i |
| Spartan-6 xc6slx45-2 |
1364 | 8 | 3 | 223 | 30 | 75 | 11.2i |
| Virtex-4 xc4vfx12-12 |
2690 | 8 | 3 | 222 | 30 | 92 | 9.2.02i |
Virtex-5 |
1534 | 4 | 3 | 222 | 30 | 113 | 9.2.02i |