Xilinx results optimized for speed and configured for operation with IN 1 - 512 bytes dual buffered and OUT 1 - 512 bytes dual buffered. uP data width: 32-bit; USB data width: 16-bit.
| Xilinx Devices | Slices | BRAM | IOB | Fmax clk usb | Fmax clk up | ISE |
| Spartan-3E 3S1600E-5 |
2951 | 8 | 222 | 30 MHz | 61 MHz | 12.2i |
| Spartan-6 6SLX100-3 |
1249 | 8 | 223 | 30 MHz | 100 MHz | 12.2i |
| Virtex-5 5VSX95T-2 |
1676 | 8 | 222 | 30 MHz | 147 MHz | 12.2i |
Virtex-6 |
1308 | 8 | 222 | 30 MHz | 201 MHz | 12.2i |