CAST USBHS-OTG-SD Core — Altera Implementation Results

The following are sample Altera results optimized for area and configured for operation with IN 1 - 1024 bytes single buffered and OUT 1 - 1024 bytes single buffered. Endpoint size 512 bytes double buffered for Cyclone-III device.

Altera Devices LEs / ALUTs MEM bits MEM
Blocks
Fmax
(uP clock)
Fmax
(usb clock)
Cyclone
EP1C20-6
3980 19200 9 M4Ks 43 MHz 56 MHz
Cyclone-III
EP3C80-6
4471 32768 6 M9Ks 105 MHz 30 MHz
Stratix
EP1S10-5
3980 19200 9 M4Ks 60 MHz 58 MHz
Stratix II
EP2S15-3
3353 19200 9 M4Ks 82 MHz 91 MHz

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