- USBSS-DEV – a device controller that conforms to the USB 3.0 SuperSpeed specification, and enables data transfers up to 5 Gbps while also reducing power requirements.
- USBHS-DEV – a complete high/full-speed (480/12 Mbps) peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s microprocessor on the other.
- USBFS-DEV - a USB Device Controller that provides USB full and low speed function interface that meets the 2.0 revision of the USB specification.
- USBHS-OTG-SD - a hi-speed USB OTG port that can serve as a host (for a single device) or as a peripheral when connected to other USB devices.
- USBHS-OTG-MPD - a hi-speed USB port that can serve as either a host or a peripheral when connected to other USB devices. It features an integrated direct memory access (DMA) controller for efficient, autonomous data transfer, and can support USB hubs and multiple peripheral devices in host mode.
For an excellent USB overview, see Which version of USB is right for your application?, by Dan Harmon, at Planet Analog
USB IP Core USBHS-HUB USB Hi-Speed Embedded Hub Controller Core
The USBHS-HUB core implements a hi-speed configurable USB Hub controller that can serve as an interface between a USB host and multiple USB peripheral devices, each operating at different signaling frequencies: Low-, Full-, or High-Speed.
The main functional features of the core include connectivity behavior, connect/disconnect detection, power management, bus fault detection and recovery, as well as support for USB transactions. The core contains the Transaction Translator module that translates Hi-Speed upstream port transactions to Low-/Full-Speed downstream ports transactions.
The USBHS-HUB is a testable, microcode-free design developed for reuse in ASICs and FPGAs. A complete test environment helps designers verify the functioning and compliance of the core. Its wide range of configurable features allows customization and optimization for a specific design. The controller is strictly synchronous with positive-edge clocking, a synchronous reset, and no internal tri-states.
- Complies with the USB 2.0 specification
- Supports Hi-Speed, Full-Speed or Low-Speed peripheral devices
- Supports standard and hub-specific requests
- Supports up to 127 downstream ports
- Integrated Transaction Translator for USB Low-/Full-Speed transfers
- Connect/disconnect detection of downstream ports
- Suspend/resume power management functions
- Supports 8-/16-bit UTMI+ Transceiver Macrocell Interface
- Optional 8-bit ULPI Transceiver Macrocell Interface on downstream port
- Broadens the host controller functionality by allowing connection of Full- and Low-Speed devices without separate
- OHCI or UHCI host controllers
- Ability for direct on-chip connection to the host without using an external transceiver
- User configurable features
- Wide range of applications
- Configurable size of the On-Chip Transfer Descriptor memory
- Number of downstream ports
- Number of transaction translator buffers
- Personal computers
- Docking stations
- Set top boxes
- Personal Digital Assistants (PDAs)
- Mobile phones
The core is partitioned into modules as shown on the block diagram and described below.
Contains endpoint0 (EP0) that is used to handle all hub-specific control transfers and endpoint1 (EP1), and the Status Change endpoint which is used to provide status change notifications to the host system. All standard and hub-class specific commands are processed by the configuration/ enumeration Finite State Machine (FSM) that is based on the contents of the ROM memory with the HUB descriptors.
Handles USB 2.0 Split Transactions by providing support for Low-/Full-Speed devices connected to the USBHS-HUB downstream ports. It supports all types of USB transfers (bulk, interrupt, control and isochronous).
Handles detection/generation of the USB reset and USB suspend/resume signals. Upstream port logic provides two interfaces - an UTMI interface, which can be connected to an external transceiver, and an UTMI+ interface, which can communicate directly with the USB host controller.
Port Routing Logic
Used to route Low-/Hi-Speed packets between downstream ports and the upstream port, as well as distribute Low-/Full-Speed packets between downstream ports and Transaction Translator.
Contains downstream FSM logic, which is responsible for device connection and speed detection, suspend/resume signaling, and USB reset signaling.
The USBHS-HUB IP core is integrated with a USB Hi-Speed host via an UTMI+ interface to allow connection of Full-/Low-Speed peripheral devices without the OHCI or UHCI companion host controller.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive simulation using a large set of test vectors and reference results, and through rigorous code coverage measurements.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:
- HDL RTL source code
- An example chip implementation, which uses the core in a sample system
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including external endpoint buffers, a bus/behavioral model USB stimulator (PHY), and a clock generator
- Simulation scripts, vectors, and expected results
- Synthesis script
- Comprehensive user documentation, including detailed specifications, a system integration guide and a verification specification