Sample results optimized for area (uP clock = 66 MHz) using a typical configuration of the CUSB2 core for a 16-bit USB 2.0 transceiver data bus (UTMI clock = 30 MHz), 32-bit CPU and Slave FIFO buses. This typical configuration includes endpoint 0 and two additional double buffered, 1024-byte endpoints, IN and OUT, as might be used for a USB mass storage device.
| ASIC Technology |
Approximate Area |
| TSMC 0.13 µm | 16,800 gates |
| TSMC 90 nm |
16,550 gates |