The following sample Altera results were optimized for area and use a minimum configuration for a 16-bit USB 2.0 transceiver data bus (UTMI clock = 30 MHz), a 32-bit processor interface and a 32-bit slave FIFO data bus. This typical minimum configuration includes endpoint 0, 1 IN 1024 bytes and 1 OUT 1024 bytes BULK double buffered end-points, as might be used for a USB mass storage device.
Altera Devices |
LE/ALUT |
Memory | IOB (assuming all I/Os are routed off-chip) |
Fmax |
Quartus Version |
| Cyclone-III EP3C16-6 |
3172 | 8 M9Ks | 259 | 100 MHz | 9.0 |
| Stratix-IV EP4SGX70-2 |
2010 | 8 M9Ks | 259 | 151 MHz | 9.0 |
| Arria GX-II EP2AGX45-4 |
2010 | 8 M9Ks | 259 | 131 MHz | 9.0 |