USB IP Core USBHS-DEV High Speed USB Device Controller Core

On this page: Description | Implementation Results | Features | Applications | Software | Block Diagram | Deliverables

The USBHS-DEV core implements a complete high/full-speed (480/12 Mbps) peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s microprocessor on the other. It is user-configurable for up to 15 IN and OUT endpoints, and includes power management and remote wake-up functions.

Options include a protocol aware DMA controller, support for a variety of widely used bus interfaces, and a UTMI Low Pin Interface (ULPI).

Designed for easy reuse in ASIC and FPGA implementations, the microcode-free design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Features

• Full compliance with the USB 2.0 specification
• Control endpoint 0 — fixed 64 Bytes size
• Configurable for up to 15 IN and 15 OUT endpoints
  • Configurable/programmable number and size of endpoints
  • Configurable/programmable single, double, triple or quad buffering
  • Programmable type of endpoints
• UTMI Transceiver Macrocell Interface. Optional UTMI Low Pin Interface (ULPI).
• Choice of different microprocessor interfaces:
  • AMBA® AHB
  • PVCI
  • Generic
• Configurable 8-, 16-, or 32-bit microprocessor interface
  • Easy integration with a wide range microprocessors and bus architectures
  • Interrupt request signals for application microprocessor
  • Interrupt vector for autovectored interrupts
• Direct access to the endpoints buffers via configurable 8-, 16-, or 32-bit Data Interface
  • Ready for external DMA module
• Synchronous RAM interface for FIFOs
• Optional protocol-aware DMA controller with configurable number of channels
• Suspend and resume power management functions
• Remote Wake-Up function
• Optional software stack
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)

Applications

The USBHS-DEV can be utilized in a variety of serial interface applications including:

• Embedded microcontroller systems
• Communication & networking systems
• Digital Media controllers

Software

A complete software stack with the most popular device classes is available. It has been designed for portability in a variety of embedded applications. It includes an intuitive Application Programming Interface (API) for application development.

Block Diagram

Deliverables

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including external FIFOs, buffers, models of interfaces, vectors for testing the core, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Software | Block Diagram | Deliverables

Download PDF datasheets for more info: ASIC | Actel | Altera | Lattice | Xilinx

This core is sourced from the IP experts at Evatronix SA.