USB IP Core USBFS-DEV USB Full-Speed Device Controller Core

On this page: Description | Implementation Results | Features | Applications | Software | Block Diagram | Functional Description | Deliverables

The USBFS-DEV is a USB Device Controller that provides USB full and low speed function interface that meets the 2.0 revision of the USB specification. The USBFS-DEV logic handles bytes transfer autonomously and bridges USB interface to a simple read/write parallel interface. The USBFS-DEV can be customized and optimized for a specific application. It contains a set of Special Function Registers that is similar to the Cypress EZ-USBTM FX chip.

The microcode-free design was developed for reuse in ASICs and FPGAs. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. Scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Features

• Support for Full and Low Speed operation according to the USB 2.0 specification

• Generic system bus interface
  

• Serial Interface Engine

• Support full speed devices
• Extraction clock and data signals in internal DPLL
• NRZI decoding/encoding
• Bit stuffing/stripping
• CRC checking/generation
• Interface for an external transceiver
• Up to 31 configurable endpoints
• Support control transfers by endpoint 0
• Support bulk, interrupt and isochronous transfers
• Double buffering for isochronous endpoints
• Programmable double buffering for bulk and interrupt endpoints
• Automatic data retry mechanism
  
• Data toggle synchronization mechanism
  
• Suspend and resume power management functions
  
• Remote Wake-Up function
  
• Endpoint buffers RAM interface
  • Up to 2 x 1024 byte FIFO size for double buffered isochronous endpoints
  • Up to 64 Bytes buffer size for each bulk, interrupt and control endpoints
• Microcontroller interface
  • 8-bit data bus interface
  • Interrupt request signals for application microcontroller
  • Interrupt vector for autovector interrupts
• DMA (optional)
• Up to 32-bit address bus width
• 8/16/32-bit configurable data bus width
• Big or little endian byte ordering

Optional Features

• Software stack
• On-Chip Peripheral Bus interface

Applications

The USBFS-DEV can be utilized to provide a USB full speed function interface in a variety of applications including:

• Mass storage
  
• Audio
  
• Communication devices
  
• Digital cameras
  
• Networking
  
• Digital media controllers

Software

A complete software stack with the most popular device classes is available. It has been designed for portability in a variety of embedded applications. It includes an intuitive Application Programming Interface (API) for application development.

Block Diagram

Functional Description

The USBFS-DEV core is partitioned into modules as shown in the block diagram and described below:

Serial Interface Engine (SIE)

The SIE logic contains a Digital Phase Locked Loop (DPLL) that uses 4 times over-sampling of the USB data stream for clock extraction. The SIE performs serial data decoding/encoding, bit stuffing/stripping and CRC checking/generation. Received/transmitted data are grouped in bytes and transferred to/from the USBFS-DEV endpoint buffer RAM.

Parallel Interface Engine (PIE)

The PIE contains a set of Special Function Registers (SFR) that are provided to control the USBFS-DEV behavior, the logic that handles all USB transfers and interfaces for endpoints buffers and for the microcontroller.

Port controller (PORTCTRL)

The port control module contains multiplexers and address decoders. The PORTCTRL logic handles all microprocessor and DMA read and write accesses to/from the Special Function Registers and endpoint buffer RAM.

DMA

The DMA module transfers byte data between endpoint buffers and external memory. The processor initializes the DMA by writing to the DMA Special Function Registers.

DMA wrapper (DMA WRAP)

The DMA wrapper generates read/write strobes for external asynchronous RAM.

Clock controller (CLKCTRL)

This module is provided to support suspend-resume control. The clock control logic uses a clock gate to switch off the USBFS-DEV clock in suspend state.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external endpoint buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide

 

On this page: Description | Implementation Results | Features | Applications | Software | Block Diagram | Functional Description | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Lattice | Xilinx

This core is sourced from the IP experts at Evatronix SA.