UDPIP-1G/10G Core — XILINX FPGA Results

UDPIP-1G/10G reference designs have been evaluated in a variety of technologies. The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core.

 

Family

UDP

Channels

Slices

Fmax (MHz)

RAM Blocks

Virtex-6

XC6VLX75T-1

1

4

1,523

1,727

152

125

3 RAMB36 + 1 RAMB18

3 RAMB36 + 5 RAMB18

Artix-7

XC7A100T-1

1

4

1,553

1,701

128

136

3 RAMB36 + 1 RAMB18

3 RAMB36 + 5 RAMB18

Virtex-7

XC7V330-1

1

4

1,650

1,780

163

156

3 RAMB36 + 1 RAMB18

3 RAMB36 + 5 RAMB18

Table 1: UDPIP-1G/10G Sample Results for the core configured with a 32bit data-path (suitable for 1Gbps), ARP, ICMP, IGMP, Rx and Tx

 

Family

UDP

Channels

Slices

Fmax (MHz)

RAM Blocks

Virtex-6

XC6VLX75T-1

1

4

1,800

1,902

140

141

3 RAMB36 + 1 RAMB18

3 RAMB36 + 5 RAMB18

Artix-7

XC7A100T-1

1

4

1,853

2,264

125

126

3 RAMB36 + 1 RAMB18

3 RAMB36 + 5 RAMB18

Virtex-7

XC7V330-1

1

4

1,931

2,278

178

156

3 RAMB36 + 1 RAMB18

3 RAMB36 + 5 RAMB18

Table 2: UDPIP-1G/10G Sample Results for the core configured with a 64bit data-path (suitable for 10Gbps), ARP, ICMP, IGMP, Rx and Tx

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