UDPIP-1G/10G Core — XILINX FPGA Results

The UDPIP-1G/10G can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family / Device

UDP

Channels

LUTs

BRAM Tiles

Fmax (MHz)

Ethernet Speed

Spartan 7

xc7s50-1

1
3,652
3

125.00

10/100/1000

4
4,929
5

Kintex U

xcku025-2

1
3,523
3

312.59

10/100/1000 and 10G

4
4,778
5

Kintex UP

xcku9p-1

1
3,678
3

312.50

10/100/1000 and 10G

4
4,988
5

Table 1:Sample Results for the core configured with a 32bit data-path, ARP, ICMP, IGMP, Rx and Tx, and without DHCP and VLAN support

 

Family / Device

UDP

Channels

LUTs

BRAM Tiles

Fmax (MHz)

Ethernet Speed

Spartan 7

xc7s50-2

1
5,095
6

156,25

10/100/1000 and 10G

4
6,416
10

Kintex U

xcku025-1

1
4,999
6
4
6,299
10

Kintex UP

xcku9p-1

1
4,957
6.5
4
6,258
10

Table 2: Sample Results for the core configured with a 64bit data-path, ARP, ICMP, IGMP, Rx and Tx. and without DHCP and VLAN support

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