UDPIP-1G/10G Core — ASIC Implementation Results

The UDPIP-1G/10G can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

UDP

Channels

ASIC
Technology

Eq. NAND2 gates

Fmax (MHz)

Memory
(Bytes)

1

TSMC 65nm

28,926

333

16,640

1

TSMC 90nm

26,782

333

16,640

4

TSMC 65nm

36,308

333

24,832

4

TSMC 90nm

33,594

333

24,832

Table 1: UDPIP-1G/10G Sample Results for the core configured with a 32bit data-path (suitable for 1Gbps), ARP, ICMP, IGMP, Rx and Tx

UDP

Channels

ASIC
Technology

Eq. NAND2 gates

Fmax (MHz)

Memory
(Bytes)

1

TSMC 65nm

39,181

333

33,024

1

TSMC 90nm

36,961

333

33,024

4

TSMC 65nm

48,528

333

49,408

4

TSMC 90nm

45,625

333

49,408

Table 2: UDPIP-1G/10G Sample Results for the core configured with a 64bit data-path (suitable for 10Gbps), ARP, ICMP, IGMP, Rx and Tx

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