UDPIP-1G/10G Core — Altera Implementation Results

UDPIP-1G/10G reference designs have been evaluated in a variety of technologies. The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core.

Family

UDP

Channels

ALMs

Fmax (MHz)

Memory Bits

Arria-V

5AGXMB1G6F40C6

1

4

2,456

3,187

136

134

100,352

172,032

Cyclone-V

5CGXFC9E6F35C7

1

4

2,490

2,245

137

129

100,352

172,032

Stratix-V

5SEE9H40C4

1

4

2,380

3,091

219

241

100,352

172,032

Table 1: UDPIP-1G/10G Sample Results for the core configured with a 32bit data-path (suitable for 1Gbps), ARP, ICMP, IGMP, Rx and Tx

 

Family

UDP

Channels

ALMs

Fmax (MHz)

Memory Bits

Arria-V

5AGXMB1G6F40C6

1

4

3,157

3,975

136

128

100,352

172,032

Cyclone-V

5CGXFC9E6F35C7

1

4

3,131

3,999

126

125

100,352

172,032

Stratix-V

5SEE9H40C4

1

4

3,060

3,900

209

207

100,352

172,032

Table 2: UDPIP-1G/10G Sample Results for the core configured with a 64bit data-path (suitable for 10Gbps), ARP, ICMP, IGMP, Rx and Tx

close window