Ethernet MAC IP Core UDPIP Hardware UDP/IP Stack Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Deliverables

Implements a User Datagram Protocol (UDP) transport layer stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the demanding task of UDP/IP encapsulation from a host processor, and enables media streaming even in processor-less SoC designs. The configurable core can operate as a full-duplex Transmitter/Receiver, or just as a Transmitter or a Receiver to minimize its silicon footprint.

Trouble-free network operation is ensured through run-time programmability of all the required network-parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and Ping, the Echo Request and Reply Messages of the Internet Control Message Protocol (ICMP) widely used to test network connectivity.

The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or optionally via registers mapped on an SoC bus. The AMBA® AXI4-Stream or the Avalon®-ST streaming protocols and the AMBA AHB and AXI, Avalon-MM, or Wishbone SoC bus protocols are supported. The core is Ethernet MAC-independent, but is available pre-integrated with CAST, Altera, Xilinx, or other third-party eMAC core.

See representative implementation results (each in a new pop-up window):

Features

Complete UDP/IP Stack in Hardware

• 10/100/1000 Ethernet support
• 10Gbit Ethernet (10GbE) support
• IPv4 support without packet fragmentation
• Transmit and Receive
• ARP with Cache
• ICMP (Ping Reply)
• UDP/IP Unicast or Broadcast
• UDP Port Filtering
• UDP/IP Checksums generation and validation, and optional Ethernet CRC validation
• Ethernet Framing processing for non-UDP user-provided packets
• Optional DHCP client

Trouble-Free Network Operation

• Run time programmable network parameters:
• Local, Destination and Gateway IP address
• Source and Destination UDP ports
• MAC address
• ARP for smooth operation in multiple-access networks
• Ping support for testing network connectivity

Easy SoC Integration

• Flexible packet data interface:
• 8- to 16-bits wide streaming capable using either AMBA AXI4-Stream or Avalon-ST, or
• Optional 32-bits wide AHB, AXI, Avalon-MM or Wishbone SoC buses
• eMAC-independent; works with CAST, FPGA vendor, or third-party MACs
• Separate clock domains for packet processing and control/data interfaces
  
• Configurable buffer sizes
• Rich interrupt support for system events

Additional Options for Faster SoC Development

• Available pre-integrated with:
• CAST, Altera, Xilinx, or other third-party eMAC core
• Media codec cores, e.g. the CAST H.264 Video Encoder

Applications

• Video, image and audio streaming or broadcasting over Ethernet, in devices such as
  
• IP cameras compatible to GigE Vision, ONVIF, or PSIA standards
  
• VOIP and smart phones
  
• High speed communication between LAN nodes

Block Diagram

 

Functional Description

The UDPIP core receives and transmits UDP packet data, and forwards other traffic from the Ethernet MAC to the application and vice versa. It also receives and transmits ARP requests and responses, and responds to ICMP echo reply messages.

The core generates and validates the UDP and IP checksums of outgoing and incoming packets, respectively. It can optionally also validate the Ethernet CRC. The core can be programmed to discard or forward corrupted packets to the user application.

The core consists of the following modules:

The Ethernet Frame Decoder receives Ethernet frames from an external Ethernet MAC, detects the frame type, and sends frames to the ARP or the IP packet decoder. Optionally, the block can also check the Ethernet CRC.

The Ethernet Frame Transmitter provides the external Ethernet MAC interface. The transmitter also multiplexes ARP and IP transmit packets from the core subsystems.

The Packet Receiver Module receives IP packets and handles them according to the packet type. The module consists of two main parts, an ICMP/UDP/IP Packet Decoder and a Received Packet Buffer.

The ICMP/UDP/IP Packet Decoder receives IP packets and buffers packet data. Decoded packets are stored in the Rx Packet Buffer and then passed to the user application. ICMP Packets are decoded and passed to the Packet Transmit Module for reply transmission.

The Received Packet Buffer implements separate data storage for the UDP application data and other data, and its size is configurable at synthesis time.

The Packet Transmit Module assembles UDP and ICMP packets. The UDP application data as well as the ICMP packet data are stored in the transmit buffer, the size of which is configurable at synthesis time.

The ARP Module receives ARP packets and handles the packets according to commands in the packet. It sends ARP packets when address resolution is requested from the Packet Transmit module.

Finally, the Control and Status Registers block controls the core’s functionality and reports its status  

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation. The RTL version includes:

• Verilog RTL source code
• Sophisticated self-checking Testbench 
• Simulation scripts, test vectors, and expected results
• Synthesis script
• Comprehensive user documentation

 

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx