Complete UDP/IP Hardware Stack
- 10/100/1000 and 10G Ethernet
- IPv4 support without packet fragmentation
- Transmit and Receive
- ARP with Cache
- ICMP (Ping Reply)
- IGMP v3 (Multicast)
- UDP/IP Unicast, and Multicast
- UDP Port Filtering
- UDP/IP Checksums generation and validation, and optional Ethernet CRC validation
- Ethernet Framing processing for non-UDP user-provided packets
- Optional DHCP client
Trouble-Free Network Operation
- Run time programmable network parameters:
- Local, Destination and Gateway IP address
- Source and Destination UDP ports
- MAC address
- ARP support for operation in networks with Dynamic IP allocation
Easy SoC Integration
- Flexible packet data interface:
- 8/16/32bit-wide streaming capable, Avalon-ST or AXI4-Stream, or
- Optional 32bit-wide AHB, AXI, Avalon-MM or Wishbone SoC busses
- Control/Status interface
- Separate clock domains for packet processing and control/data interfaces
- Configurable buffer sizes
- Rich interrupt support for system events
- Available pre-integrated with:
- CAST, Altera, Xilinx, or other third-party eMAC core
- CAST Image and Video compression cores
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PDF Datasheets
Related Information
News Releases
- 05/16/13, Ultra-Low Latency H.264 Video Encoding Now Available from CAST
- 02/19/13, CAST Adds Multicast and AXI to UDP/IP Core for Streaming Media Systems
- 12/15/11, CAST Full Hardware UDP/IP Stack Core Simplifies Streaming Media Over IP Networks
Related Products
Get SoC development and performance benefits by combining this UDP/IP Stack Core with any of these additional CAST cores:
- MAC-1G: 1-Gigabit Ethernet Media Access Controller
- MAC-1G-L: Lite 1-Gigabit Ethernet MAC
- MAC: 10/100 Ethernet MAC
- MAC-L: Lite 10/100 Ethernet MAC
- Image and Video Compression IP cores: H.264/AVC video, JPEG 2000, JPEG, and more.
- H2642RTP Hardware RPT Stack for H.264
Contact CAST Sales to discuss how our IP integration services can save you even more time with any of these multi-core combinations.
Ethernet MAC IP Core UDPIP UDP/IP Hardware Protocol Stack Core
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming even in processor-less SoC designs. The core can be configured to operate as a full-duplex Transmitter/Receiver, or as Transmitter-only or Receiver-only to minimize silicon footprint.
Trouble-free network operation is ensured through run-time programmability of all the required network-parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity.
The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming -capable interfaces, or optionally via registers mapped on an SoC bus. The AMBA® AXI4-stream or the Avalon®-ST streaming protocols and the AMBA AHB and AXI, Avalon-MM, or Wishbone SoC bus protocols are supported. The core is Ethernet MAC-independent, but is available pre-integrated with CAST, Altera, Xilinx, or other third-party eMAC core.
See representative implementation results (each in a new pop-up window):
Applications
- Video, image and audio streaming or broadcasting over Ethernet, in devices such as
- IP cameras compatible to the GigE Vision, ONVIF, or PSIA standards
- VOIP and smart phones
- High speed communication between LAN nodes
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Deliverables
The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation. The RTL version includes:
- Verilog RTL source code
- Sophisticated self-checking Testbench
- Simulation scripts, test vectors, and expected results
- Synthesis script
- Comprehensive user documentation
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