UDPIP-40G Core — XILINX FPGA Results

The UDPIP-40G can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family / Device

UDP

Channels

LUTs

BRAM Tiles

Fmax (MHz)

Kintex Ultrascale

xcku115-2
1
8,492
20

312.50

4
11,049
32

Kintex Ultrascale+

xcku15p-1
1
8,456
20
4
11,057
32

Virtex Ultrascale+

xcvu11p-1
1
8,450
20
4
11,041
32

Table 1:Sample Results for the core configured with ARP, ICMP, IGMP, Rx and Tx. and without DHCP and VLAN support

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