UDPIP-40G Core — ASIC Implementation Results

The UDPIP-40G can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

UDP Channels

ASIC Technology

Eq. NAND2 Gates

Fmax (MHz)

Memory (Bytes)

1

TSMC 65nm

42,011

333

48kB

1

TSMC 90nm

40,269

333

96kB

4

TSMC 65nm

47,552

333

48kB

4

TSMC 90nm

45,170

333

96kB

Table 1: UDPIP-40G Sample Results for the core configured with a 256-bit AXI4-Stream data-path, ARP, ICMP, IGMP, Rx and Tx.

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