UDPIP-40G Core — Intel Implementation Results

The UDPIP-40G can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family

UDP Channels

ALMs

Fmax (MHz)

Memory Bits

Stratix-V
5SGTMC5K2F40C1

1

4

7,429

9,236

314

332

Arria-10 10AX090N1F45E1

4

9,087

344

Table 1: UDPIP-40G Sample Results for the core configured with a 256-bit AXI4-Stream data-path, ARP, ICMP, IGMP, Rx and Tx.

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