Complete UDP/IP Hardware Stack
- 1/10/40G Ethernet
- IPv4 support without packet fragmentation
- Jumbo and Super Jumbo Frames
- Transmit and Receive
- ARP with Cache
- ICMP (Ping Reply)
- IGMP v3 (Multicast)
- UDP/IP Unicast, and Multicast
- UDP Port Filtering
- UDP/IP Checksums generation and validation, and optional Ethernet CRC validation
- VLAN (IEEE 802.1Q) support
- 1 to 32 UDP transmit and 1 to UDP 32 receive channels
- Ethernet Framing processing for non-UDP user-provided packets
- DHCP client
Trouble-Free Network Operation
- Run time programmable network parameters:
- Local MAC address, Local IP address, Gateway IP address, and IP subnet mask
- Per channel: Destination IP address, Source and Destination and filtered UDP ports, multicast enable/disable and receive group
- ARP support for operation in networks with Dynamic IP allocation
Easy SoC Integration
- Flexible interfaces:
- Packet Data: 256-bit streaming capable using Avalon-ST or AXI4-Stream
- Control/Status Registers: Generic 32-bit SRAM-like, or optionally 32-bit AHB, AXI, Avalon-MM or Wishbone
- Separate clock domains for packet processing and control/status interfaces
- Configurable buffer sizes
- Rich interrupt support for system events
- Optionally pre-integrated with Intel, Xilinx, or other third-party 40G eMAC core
Call or click.
- UDPIP-1G/10G UDP/IP Hardware Protocol Stack
- H2642RTP: Hardware RTP stack for H.264
- RTP2H264: Hardware RTP Stack for H.264 Stream Decapsulation
- JPEG2H264: Hardware RTP Stack for JPEG Encoders
- Image and Video Compression IP cores: H.264/AVC video, JPEG 2000, MPEG2, JPEG, and more.
Contact CAST Sales to discuss how our IP integration services can save you even more time with any of these multi-core combinations.
UDPIP-40G 40G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 40Gbps even in processor-less SoC designs.
Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN.
The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or optionally via registers mapped on an SoC bus. The AMBA® AXI4-stream or the Avalon®-ST streaming protocols and the AMBA AHB and AXI, Avalon-MM, or Wishbone SoC bus protocols are supported. The core is Ethernet MAC-independent, and can be pre-integrated with Intel, Xilinx, or other third-party 40G eMAC core.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
Video, image and audio streaming or broadcasting over Ethernet, in devices such as IP cameras compatible to the GigE Vision, ONVIF, or PSIA standards, VOIP and smart phones. Also high-frequency trading systems, high-speed communication between LAN nodes, device monitoring, and control over IP networks.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.