CAST SPI_MS Core — ASIC Implementation Results

Results with the core configured for a 16-bit data path and 2 FIFOs (RX/TX) of 64x18 bits.

ASIC Technology

Fmax (MHz)

Logic Area¹ (µm²)

Number of eq. gates²

Memory
(SRAM bits)

TSMC 0.18 µm

350

43,100

4,320

2x64x18

TSMC 0.13 µm

420

20,730

4,070

2x64x18

TSMC 0.09µm

520

10,560

3,740

2x64x18

¹ Excluding memory
² Equivalent gate count uses the smallest NAND2 gate available for the technology used

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