CAST SPI_MS Core — Altera Implementation Results

Results with the core configured for a 16-bit data path and 2 FIFOs (RX/TX) of 64x18 bits.

Altera Devices LEs/LUTs
 Memory External
I/Os 		Fmax
(MHz)		 Quartus
Cyclone
EP1C2-6		 520 2 M4Ks 67 190 7.2
Cyclone-II
EP2C35-6		 549 2 M4Ks 67 200 7.2
Cyclone-III
EP3C40-6		 565 2 M9Ks 67 208 7.2
Stratix
EP1S20-5		 526 2 M4Ks 67 195 7.2
Stratix-II
EP2S60-3		 467 2 M4Ks 67 260 7.2
Stratix-III
EP3S50-2		 468 2 M9Ks 67 265 7.2

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