Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream

Octal SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Data Link Controllers
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES, programmable
Key Expander

DES single
DES triple

Hash Functions
SHA-3 (Keccak)

Enables an external device to have full access to the internal AHB-Lite bus over an SPI connection.

Typical Use Cases

  • Firmware upload over SPI
  • Monitor and Control over SPI
    • e.g., Analog Front End and, or MEMs initialization and calibration, over SPI
  • Debug Over SPI


  • SPI-Slave Interface
    • Single and Dual serial data lines
    • 32-bit SPI transfers
    • Fixed transmission format for lower area and power
  • AHB-Lite Master Interface

Ease of Integration

  • Independent serial and system (AHB bus) clocks
    • System clock must be at least 2.4x faster than the serial clock
  • CDC-Clean design: Signals crossing clock domains are doubled buffered in the destination domain
  • Bus Error Reporting
    • Core monitors the AHB Lite bus and reports to erroneous transfers and error type to the system


  • Verilog RTL source code or targeted FPGA netlist
  • User Documentation
  • Sample synthesis and simulation scripts

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Downloads (PDFs)

Related Products

  • OSPI-XIP-AHB Single, Dual, Quad, & Octal SPI Flash Controller for AHB
  • QSPI-XIP-AHB Quad SPI Bus Controller with XIP, for AHB
  • QSPI-XIP-AXI Quad SPI Bus Controller with XIP, for AXI
  • QSPI-APB Quad-Bit Serial Peripheral Interface Master/Slave
  • SPI-APB Serial Peripheral Interface Master/Slave

More Information

SPI2AHB SPI to AHB-Lite Bridge

The SPI2AHB core implements an SPI Slave to AHB-Lite Master bridge. This allows an external Serial Peripheral Interface (SPI) bus master to perform read or write access to any memory-mapped device on the internal AMBA® AHB-Lite bus.

SPI Bus IP cores icon at CAST Inc.The core implements a simple over-SPI protocol to convert SPI transactions into AHB Read or Write instructions. This over-SPI protocol supports only 32-bit-wide data accesses, which are translated to AHB-Lite accesses on the AHB-Lite master port. The bridge also monitors the AHB-Lite bus and reports erroneous transfers to the system. Errors captured by the core include Error Responses on the AHB bus, and errors due to slow responses for the accessed AHB-Lite slave.  

The core supports both dual and single SPI data lines. The format of the lower level SPI transmission is compliant to the SPI de facto standard, but fixed to minimize area and power. The core drives the outbound serial data on the rising edge of the serial clock, and samples inbound serial data on the negative edge of the serial clock (CPHA=1), while the resting state of the serial clock is low (CPOL=0). Furthermore, all SPI transactions are assumed to be 32-bit wide.

The SPI2AHB core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. It is available in Verilog RTL source or as a targeted FPGA netlist, and its deliverables include sample synthesis and simulation scripts and comprehensive user documentation.

Block Diagram

SPI2AHB SPI to AHB-Lite Bridge Block Diagram


The SPI2AHB enables an external device to have full access to the internal AHB-Lite bus over a simple SPI connection. It can be used for firmware uploads, design-initialization, and run-time monitor, control and debug in a wide variety of designs including typical microcontrollers, sensors, MEMs, and analogue front-ends.


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


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