Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • Controls high-speed, synchronous, serial communication
    • Motorola Serial Peripheral Interface (SPI) format support
    • TI Synchronous Serial Frame format support
  • Master or Slave mode; controls up to four slaves in Master mode
    • Separate SCLK input for Master Mode
    • Asynchronous Slave Interface
  • Single, Dual and Quad-bit modes
  • Full duplex operation; half-duplex support
  • Compatible with many industry-standard serial Flash devices
  • Execute in Place (XIP) mode
  • AMBA® AHB interface
  • DMA Interface
  • 4-bit to 32-bit serial TX/RX
  • 8 to 256 word TX/RX FIFO, configurable
  • Interrupt control
  • LSB or MSB mode
  • National Microwire Frame format support

Contact Sales
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+1 201.391.8300

Downloads (PDFs)

Related Products

  • OSPI-XIP-AHB Single, Dual, Quad, & Octal SPI Flash Controller for AHB
  • QSPI-XIP-AXI Quad SPI Bus Controller with XIP, for AXI
  • QSPI-MS Quad-Bit Serial Peripheral Interface Master/Slave
  • SPI-MS Serial Peripheral Interface Master/Slave
  • SPI2AHB SPI to AHB-Lite Bridge
  • PFLASH-CTRL Parallel NOR Flash Controller

More Information

QSPI-XIP-AHB Quad SPI Bus Controller with XIP, for AHB

The QSPI-XIP-AHB core implements a quad Serial Peripheral Interface (SPI) module that either controls a serial data link as a master, or reacts to a serial data link as a slave.   

Users can configure the core via software control to be a master or slave device.  In master mode, it can be used with up to four SPI slave devices.

SPI Bus IP cores icon at CAST Inc.Reading and writing the core is done on the AMBA® AHB bus interface. The core operates in various data modes from 4 to 32 bits (eight modes are supported in multiples of four data bits). The data is then serialized and transmitted, either LSB or MSB first, using the standard four-wire SPI bus interface or the extended Dual or Quad Bus modes. 

The QSPI-XIP-AHB core is compatible with various industry-standard DMA controllers. Enabling DMA operation assists a DMA controller in the loading (writing) of the transmit FIFO, and the unloading (reading) of the receive FIFO.

The Execute in Place (XIP) Mode allows an AHB Master to directly read the contents of any of several industry-standard flash devices (such as Winbond, Macronix, Spansion, and Micron devices) simply by reading from the address space of the QSPI Controller.

Block Diagram

QSPI-XIP-AHB Quad SPI Bus Controller with XIP, for AHB Core Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

 

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