Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream

Octal SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Data Link Controllers
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES, programmable
Key Expander

DES single
DES triple

Hash Functions
SHA-3 (Keccak)

Flexible SPI Master/Slave

  • Single- or Quad-Bit Serial Interface
  • Up to four slaves under Master control; four slave-select lines of programmable polarity
  • Configurable frame format
    • 4 to 32 bit frames
    • Configurable inter-frame delay
    • MSB-first and LSB-first frames
  • Separate clock input and scaler for master serial clock generation
  • Asynchronous Master and Slave interfaces

Easy Integration

  • 32bit AMBA/APB interface
  • Asynchronous SPI and APB clocks
  • 16 word Tx and Rx FIFOs and DMA controller handshaking signals
  • Software programmable operation
  • Maskable interrupt and status registers for status reporting

Smooth Technology Mapping

  • Fully synchronous, scan-ready design architecture
  • Delivered with sample scripts, RTL test-bench and sample test-cases

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Related Products

  • OSPI-XIP-AHB Single, Dual, Quad, & Octal SPI Flash Controller for AHB
  • QSPI-XIP-AHB Quad SPI Bus Controller with XIP, for AHB
  • QSPI-XIP-AXI Quad SPI Bus Controller with XIP, for AXI
  • SPI-MS Serial Peripheral Interface Master/Slave
  • SPI2AHB SPI to AHB-Lite Bridge

More Information

QSPI-MS Serial Peripheral Interface Master/Slave

The Serial Peripheral Interface (SPI) allows high-speed synchronous serial data transfers between microprocessors, microcontrollers, and peripheral devices. The QSPI-MS core implements a controller for a single- or quad-lane Serial Peripheral Interface bus, which can operate either as a master or as a slave.

SPI Bus IP cores icon at CAST Inc.Designed to work with a wide variety of SPI-bus variants, the core supports different serial transfer (frame) formats. For example, the inter-frame delay, bit-width of frame and most-significant bit position in a frame are all software programmable. In master mode the core can control up to four slaves. A software-controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose. Under slave mode the core receives the serial clock. The master and slave clock domains are designed to be asynchronous to each other.

The controller core interacts with the host processor via an 32-bit APB slave interface that allows access to the transfer data, the control, and states registers. The APB clock is asynchronous to the SPI clocks. To ease integration, an interrupt can be generated to indicate availability of received data or availability to transmit new data. The QSPI-MS implements two 16-word FIFOs, one for the receiver and one for the transmitter path, and handshaking signals to ease operation with an external DMA controller.

The QSPI-MS core is proven and available in RTL source or as a targeted FPGA netlist.


The QSPI-MS core is suitable for implementing serial interfaces in a wide range of applications, including host communication with flash memories, and peripherals such as sensors, ADC/DACs, touchscreens, video game controllers, and audio/video codecs.

Block Diagram

qspi-ms block diagram


The QSPI-MS as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


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